1. Field of the Invention
This invention generally relates to integrated circuit (IC) design and, more particularly, to a system and method for minimizing the size of circuit die in non-critical timing paths.
2. Description of the Related Art
The size, complexity, and operating or switching speeds of semiconductor ICs have increased, while feature geometries have decreased, and interconnect systems for such ICs have dramatically increased in complexity. In a digital circuit, data is suppose to move in lockstep, advancing one stage on each tick of the clock signal. This is enforced by synchronizing elements such as flip-flops or latches, which copy their input to their output when instructed to do so by the clock.
As noted in Wikipedia, one approach that is used to analyze timing errors is to model the interconnect system as an arrangement of nets (interconnections between gate outputs and interconnected gate inputs) inter-coupled with parasitic capacitors. Static Timing Analysis (STA) is used to develop early and late arrival times (timing window) for each relevant net or node. This timing window is enlarged by a worst case assessment of crosstalk noise for both early and late arrival times using noise aware STA. This worst case timing window is used for timing analysis of all paths through the corresponding net and a list of paths that fail timing requirements are provided. In static timing analysis, the word static alludes to the fact that this timing analysis is carried out in an input-independent manner, and purports to find the worst-case delay of the circuit over all possible input combinations.
More explicitly, STA is a method of computing the expected timing of a digital circuit without performing a simulation. High-performance ICs have conventionally been characterized by the clock frequency at which they operate. Gauging the operation of a circuit at a specified speed requires an ability to measure, during the design process, its delay at numerous steps. Moreover, delay calculations must be incorporated into the inner loop of timing optimizers at various phases of design, such as logic synthesis, layout (placement and routing), and in in-place optimizations performed late in the design cycle. While such timing measurements can theoretically be performed using a rigorous circuit simulation, such an approach is liable to be too slow to be practical. Static timing analysis plays a vital role in facilitating the fast and reasonably accurate measurement of circuit timing. The main goal of static timing analysis is to verify that despite these possible variations, all signals will arrive neither too early nor too late, and hence proper circuit operation can be assured. Faster design times are a result of using simplified STA delay models, and a limited consideration of the effects of logical interactions between signals.
Also, since STA is capable of verifying every path, apart from helping locate setup and hold time violations, it can detect other serious problems like glitches, slow paths and clock skew. The critical path is defined as the path between an input and an output with the maximum delay. Once the circuit timing has been computed by one of the techniques below, the critical path can easily be found by using a traceback method. The arrival time of a signal is the time elapsed for a signal to arrive at a certain point. The reference, or time 0.0, is often taken as the arrival time of a clock signal. To calculate the arrival time, delay calculation of all the components in the path is required. Arrival times, and indeed almost all times in timing analysis, are normally kept as a pair of values—the earliest possible time at which a signal can change, and the latest.
Required time is the latest time at which a signal can arrive without making the clock cycle longer than desired. The computation of the required time proceeds as follows. At each primary output, the required times for rise/fall are set according to the specifications provided to the circuit. Next, a backward topological traversal is carried out, processing each gate when the required times at all of its fanouts are known. The slack associated with each connection is the difference between the required time and the arrival time. A positive slack (s) at a node implies that the arrival time at that node may be increased by (s) without affecting the overall delay of the circuit. Conversely, negative slack implies that a path is too slow, and the path must be sped up (or the reference signal delayed) if the whole circuit is to work at the desired speed.
The behavior of an electronic circuit is often dependent on various factors in its environment like temperature and local voltage variations, or the die size. In such a case either STA needs to be performed for more than one such set of conditions, or STA must be prepared to work with a range of possible delays for each component, as opposed to a single value. If the design works at each extreme condition, then under the assumption of monotonic behavior, the design is also qualified for all intermediate points.
The use of corners in static timing analysis has several limitations. It may be overly optimistic, since it assumes perfect tracking—if one gate is fast, all gates are assumed fast, or if the voltage is low for one gate, it's also low for all others. Corners may also be overly pessimistic, for the worst case corner may seldom occur. In an IC, for example, it may not be rare to have one metal layer at the thin or thick end of its allowed range, but it would be very rare for all 10 layers to be at the same limit, since they are manufactured independently. Statistical STA, which replaces delays with distributions, and tracking with correlation, is a more sophisticated approach to the same problem.
Conventionally, slow signal path timing errors can be corrected by using higher performance parts. Similarly, timing slack can be traded against die size. While smaller sized dice typically perform more poorly, their use can shrink the overall area of an IC. Therefore, careful designing is done to maximize the use of small die size parts in non-critical regions.
It would be advantageous if there was a systematic approach to determine if the size of die in an IC could be made smaller without impacting non-critical timing signal paths, or signal paths with excessive slack timing.